1. Field of the Invention
The present invention relates to integrated circuit memory systems, and more particularly to cache memory systems.
2. Description of the Related Art
In typical hierarchical memory systems, cache memories are small, fast memory circuits that store most-recently accessed code or data to reduce the latency (i.e., the total time between the start and completion) of references to memory. The performance of execution units or processors accessing the cache typically depends on the latency of receiving data from the cache. As integrated circuit die sizes increase and integrated circuit manufacturing process geometries decrease, the size of a cache that may be implemented on an integrated circuit die increases. In general, as cache size increases, the time to access data within the cache increases, reducing the performance benefits of using a larger cache. Thus, improved techniques for storing data in cache memories are desired.